Simulation and benchmarking of MOS varactors for the CMOS090 RF process technology

A varactor with high Q factor and large tuning range is a mandatory prerequisite for a current efficient LC-tank VCO design. Commonly used varactors include the p-n junction varactors, PMOS varactors and accumulation mode (n or ptype) varactors. This paper discusses the results from the benchmarking of different two and three-terminal MOS varactor structures. The structures are first generated through process simulation based on the CMOS090 RF process flow, which is the next RF CMOS technology for the 90nm node. High frequency AC electrical simulations with quantum mechanical corrections using the density gradient method are carried out in order to generate the Q factor and tuning range of the varactor unit cell. SPICE compact models are extracted to study the effect of large area devices, which can be represented as 3D extended netlists. The simulation results show the tradeoffs between the Q factor and tuning range dependant on the gate oxide thickness and layout parameters like finger length, finger width and the total are of the device. The advantages and disadvantages of the two and three-terminal varactor structures are discussed. The effect of finger length, finger width and the number of fingers on the Q factor and the tuning range of the varactors are analyzed using compact models. Optimal design spaces for achieving a specific varactor Q factor are proposed.